biRISC-V is a 32-bit Superscalar RISC-V CPU with the following features:
Features
- 32-bit RISC-V ISA CPU core.
- Superscalar (dual-issue) in-order 6 or 7 stage pipeline.
- Support RISC-V’s integer (I), multiplication and division (M), and CSR instructions (Z) extensions (RV32IMZicsr).
- Branch prediction (bimodel/gshare) with configurable depth branch target buffer (BTB) and return address stack (RAS).
- 64-bit instruction fetch, 32-bit data access.
- 2 x integer ALU (arithmetic, shifters and branch units).
- 1 x load store unit, 1 x out-of-pipeline divider.
- Issue and complete up to 2 independent instructions per cycle.
- Supports user, supervisor and machine mode privilege levels.
- Basic MMU support – capable of booting Linux with atomics (RV-A) SW emulation.
- Implements base ISA spec v2.1 and privileged ISA spec v1.11.
- Verified using Google’s RISCV-DV random instruction sequences using cosimulation against C++ ISA model.
- Support for instruction / data cache, AXI bus interfaces or tightly coupled memories.
- Configurable number of pipeline stages, result forwarding options, and branch prediction resources.
- Synthesizable Verilog 2001, Verilator and FPGA friendly.
- Coremark: 4.1 CoreMark/MHz
- Dhrystone: 1.9 DMIPS/MHz (‘legal compile options’ / 337 instructions per iteration)
Following are the aims of this project:
Project Aims
- Boot Linux all the way to a functional userspace environment.
- Achieve competitive performance for this class of in-order machine (i.e. aim for 80% of WD SweRV CoreMark score).
- Reasonable PPA / FPGA resource friendly.
- Fit easily onto cheap hobbyist FPGAs (e.g. Xilinx Artix 7) without using all LUT resources and synthesize > 50MHz.
- Support various cache and TCM options.
- Be constructed using readable, maintainable and documented IEEE 1364-2001 Verilog.
- Simulate in open-source tools such as Verilator and Icarus Verilog.
You can download biRISC-V here
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