Minerva is a CPU core that currently implements the RISC-V RV32IM instruction set. Its microarchitecture is described in plain Python code using the Amaranth toolbox.

 

Features

The microarchitecture of Minerva is largely inspired by the LatticeMico32 processor.

Minerva is pipelined on 6 stages:

  1. Address The address of the next instruction is calculated and sent to the instruction cache.
  2. Fetch The instruction is read from memory.
  3. Decode The instruction is decoded, and operands are either fetched from the register file or bypassed from the pipeline. Branches are predicted by the static branch predictor.
  4. Execute Simple instructions such as arithmetic and logical operations are completed at this stage.
  5. Memory More complicated instructions such as loads, stores and shifts require a second execution stage.
  6. Writeback Results produced by the instructions are written back to the register file.

 

 

Pipeline Diagram Image

The L1 data cache is coupled to a write buffer. Store transactions are in this case done to the write buffer instead of the data bus. This enables stores to proceed in one clock cycle if the buffer isn’t full, without having to wait for the bus transaction to complete. Store transactions are then completed in the background as the write buffer gets emptied to the data bus.

 

You can download the Minerva Processor core here