This repository hosts a RISC-V implementation written in SpinalHDL with MMU and Linux support.

Features

  • RV32I[M][A][F[D]][C] instruction set
  • Pipelined from 2 to 5+ stages ([Fetch*X], Decode, Execute, [Memory], [WriteBack])
  • 1.44 DMIPS/Mhz –no-inline when nearly all features are enabled (1.57 DMIPS/Mhz when the divider lookup table is enabled)
  • Optimized for FPGA, does not use any vendor specific IP block / primitive
  • AXI4, Avalon, wishbone ready
  • Optional MUL/DIV extensions
  • Optional F32/F64 FPU (require data cache for now)
  • Optional instruction and data caches
  • Optional hardware refilled MMU
  • Optional debug extension allowing Eclipse debugging via a GDB >> openOCD >> JTAG connection
  • Optional interrupts and exception handling with Machine, [Supervisor] and [User] modes as defined in the RISC-V Privileged ISA Specification v1.10.
  • Two implementations of shift instructions: single cycle (full barrel shifter) and shiftNumber cycles
  • Each stage can have optional bypass or interlock hazard logic
  • Linux compatible
  • Zephyr compatible
  • FreeRTOS port

The hardware description of this CPU is done by using a very software oriented approach (without any overhead in the generated hardware). Here is a list of software concepts used:

  • There are very few fixed things. Nearly everything is plugin based. The PC manager is a plugin, the register file is a plugin, the hazard controller is a plugin.
  • There is an automatic a tool which allows plugins to insert data in the pipeline at a given stage, and allows other plugins to read it in another stage through automatic pipelining.
  • There is a service system which provides a very dynamic framework. For instance, a plugin could provide an exception service which can then be used by other plugins to emit exceptions from the pipeline.There is a service system which provides a very dynamic framework. For instance, a plugin could provide an exception service which can then be used by other plugins to emit exceptions from the pipeline.

 

You can download VexRiscv here