YARVI2 is an FPGA-focused in-order scalar RISC-V softcore with branch prediction. The original, YARVI, was the first non-Berkely freely available RISC-V softcore implementation. YARVI2 is a complete rewrite for better performance.

YARVI2 is free and open hardware licensed under the ISC license (a license that is similar in terms to the MIT license or the 2-clause BSD license).

 

Features
  • RV32I implemented and tested
  • Eight stage pipeline
  • YAGS branch predictor, jump, call, and return address predictor
  • Current performance
    • 98.1 Dhrystones MIPS
    • 0.904 instructions/cycle (on Dhrystones)

    On a Lattice Semi ECP5 85F, speed grade 6 (as per make fmax ipc):

    • 56.6 MHz (128/128 KiB configuration)

    On an Altera Cyclone-V A9 C8

    • 100+ MHz (128/128 KiB configuration)

 

You can download YARVI here