This document by Harry H. Porter III of Portland State University introduces and explains the RISC-V standard, giving an informal overview of the architecture of a RISC-V processor. This document does not discuss a particular implementation, instead the focus is on some of the various design options that are included in the formal RISC-V specification.

 

The RISC-V project defines and describes a standardized Instruction Set Architecture (ISA). RISC-V is an open-source specification for computer processor architectures, not a particular chip or implementation. To date, several different groups have designed and fabricated silicon implementations of the RISC-V specifications. Based on the performance of these implementations and the growing need for interoperability among vendors, it appears that the RISC-V standard will increase in importance.