The MIV_RV32IMAF_L1_AHB is a softcore processor designed to implement the RISC-V instruction set for use in Microsemi FPGAs. The processor is based on Rocket-Chip, which contains a highperformance single-issue in order execution pipeline 32-bit RISC-V core. This core includes, an industrystandard JTAG interface to facilitate debug access, along with separate AHB bus interfaces for memory and IO access, Error-Correcting Code (ECC) cache memory availability and support for 31 dedicated interrupt ports.

 

Key Features:
  • Designed for low power ASIC microcontroller and FPGA soft-core implementations.
  • Integrated 8Kbytes instructions cache and 8Kbytes data cache.
  • A Platform-Level Interrupt Controller (PLIC) supports up to 31 programmable interrupts with a single priority level 0. The 31 interrupt inputs are serviced from 0 to 31 in ascending order.
  • Supports the RISC-V standard RV32IMAF ISA.
  • On-Chip debug unit with a JTAG interface.
  • Two external AHB interfaces for IO and memory.
  • Support for Error-Correcting Code (ECC) cache on RTG4 and PolarFire.

 

Supported Devices:
  • PolarFire SoC
  • SmartFusion2
  • IGLOO2
  • RTG4
  • PolarFire

 

You can order this softcore from Microsemi here