The NOEL-V is a synthesizable VHDL model of a processor that implements the RISC-V architecture. It is the first processor in our RISC-V line of processors, which complements our existing LEON line of processors.

 

The NOEL-V can be implemented as a dual-issue processor, allowing it to execute up to two instructions per cycle in parallel. To support this instruction rate, the NOEL-V has advanced branch prediction capabilities. Its cache controller supports a store buffer FIFO with one cycle per store sustained throughput and wide AHB slave support for fast stores and cache refill.

 

The NOEL-V is interfaced using the AMBA 2.0 AHB bus (a subsystem with Level-2 cache and AXI4 backend is also available) and supports the plug&play method for IP cores provided in our GRLIB IP library. The processor can be efficiently implemented on FPGA and ASIC technologies, and uses standard synchronous memory cells for caches and the register file.

 

The NOEL-V processor has the following features:

  • RISC-V 32-bit and 64-bit architecture
    • Hardware multiply and divide units
    • Compressed (16 bit) instruction support
    • Atomic instruction extension
    • 32/64 bit floating point extensions using non-pipelined area efficient FPU or high-performance fully pipelined IEEE-754 FPU
    • Machine, supervisor and user mode. RISC-V standard MMU with configurable TLB
    • RISC-V Hypervisor (H) extension (adding virtual supervisor mode and virtual user mode)
    • User level interrupts
  • Fault Tolerance
  • RISC-V standard PLIC
  • RISC-V standard PMP (physical memory protection)
  • RISC-V standard external debug support
  • Advanced dual-issue in-order pipeline
  • Dynamic branch prediction, branch target buffer and return address stack
  • Four full ALUs, two of them late in the pipeline to reduce stalls
  • Separate instruction and data L1 cache (Harvard architecture) with snooping
  • Optional L2 cache: 256-bit internal, 1-4 ways, 16 KiB – 8 MiB
  • Native AMBA 2.0 AHB bus interface, 32-, 64- or 128-bit wide.
    • Subsystem including processor and Level-2 cache with AXI4 backend also available.
  • Robust and fully synchronous single-edge clock design
  • Extensively configurable
  • Large range of software tools: compilers, kernels and debug monitors
  • High Performance*: CoreMark: 4.03** / 4.69*** CoreMark/MHz
Synthesis

The NOEL-V processor can be synthesized with common synthesis tools such as Xilinx Vivado, Synplify, and Synopsys DC. The processor model is highly portable between different implementation technologies.

 

Software development

The NOEL-V processor implements the RISC-V ISA which means that compilers and kernels for RISC-V can be used with NOEL-V (kernels will need a NOEL-V BSP). To simplify software development, we provide several prebuilt toolchains. Currently, the NOEL-V processor is supported by pre-built RTEMS and Linux toolchains. We provide VxWorks 7 BSP for NOEL-V under commercial license. Over time, the NOEL-V software support will be extended to the same level of support that exists for the LEON line of processors.

 

The GRMON monitor interfaces to the NOEL-V on-chip debug support unit, implementing a large range of debug functions including GDB support for source level debugging.

 

Configurations

The NOEL-V processor core is available as part of a subsystem that also contains system peripherals. The subsystem can be configured to use the processor configurations listed in the table below. The configurations listed below are the ones recommended by us since they are covered by regression tests. Software toolchains provided by us are developed and built considering the same configurations. It is also possible to tailor additional configuration settings to create custom processor configurations by editing the VHDL generic (configuration parameter) assignments in the subsystem.

 

Configuration Target Architecture Pipeline RISC-V extensions MMU PMP Privilege modes Example SW
HP High-performance processing 32 or 64 bits Dual issue IMAFDB*CH Yes Yes Supervisor, User and Machine + Virtualization Hypervisor, Linux, VxWorks
GP General purpose processing 32 or 64 bits Dual or single issue IMAFDB*CH Yes Yes Supervisor, User and Machine + Virtualization Hypervisor, Linux, VxWorks
GP-lite General purpose processing      Area optimized 32 or 64 bits Dual or single issue IMAFDB*C Yes No Supervisor, User and Machine Linux, VxWorks
MC Controller applications 32 or 64 bits Single issue IMAFDB*C No Yes User and Machine RTEMS
MC-lite Controller applications    Area Optimized 32 or 64 bits Single issue IMA No No User and Machine RTEMS

 

  • RV32I – 32-bit Base Integer instructions
  • RV64I – 64-bit Base Integer instructions
  • M – Hardware support for multiply and division
  • A – Atomics
  • FD – Single/Double Floating Point
  • G – short for IMAFD
  • C – Compressed instructions
  • H – Hardware hypervisor support
  • B – Bit manipulation instructions

Note: The standard configurations may be extended when additional extensions are supported by NOEL-V.

 

Availability and licensing

The NOEL-V is part of our free open source GRLIB IP Library (the pipelined GRFPUnv is a commercial-only offering and not included in the free open source distribution). NOEL-V is also available under a low-cost commercial license, allowing it to be used in any commercial application. Please see the GRLIB IP Core User’s Manual – Processor license overview for license types.