ParaNut processor is a customizable, highly scalable, and RISC-V compatible processor architecture for FPGA-based systems. The goal of the ParaNut project is to develop an open, scalable and practically applicable multi-core processor architecture for embedded systems. Scalability is given by supporting parallelism at thread and data level based on multiple processing cores while keeping the design of the individual core itself as simple as possible. ParaNut introduces a unique concept for SIMD (single instruction, multiple data) vectorization. Whereas SIMD extensions for workstation processors or embedded systems frequently contain specialized instructions leading to an inherently bad compiler support, SIMD code for the ParaNut can be programmed in a high-level language according to a paradigm very similar to thread programming. The instruction set is kept compatible to the RISC-V specification. Hence, the RISC-VGCC tool chain and libraries/operation systems (newlib, Linux in the future with some necessary extensions) can be used with the ParaNut.

 

Key aspects of the ParaNut architecture are:

 

  • Scalability and Parallelism: A special concept of parallelism combines the advantages of SIMD vectorization and simultaneous multi-threading in one architecture with a simple programming model.
  • Security: Speculation techniques are generally avoided in order to make the processor robust against security flaws.
  • SystemC as the primary language: The ParaNut hardware is modeled in SystemC and in general, the same code model is used for hardware synthesis as well as for building a cycle-accurate instruction set simulator. Only some performance-critical modules are implemented in VHDL. This ensures that the simulator reflects the real hardware behavior.

 

The design is presently used in education and research. Experiments on a Xilinx 7 platform running the CoreMark benchmark reveals an almost perfect speedup of 3.97 for a 4-core processor and a speedup of 7.6 for a ParaNut with 8 CPU cores.

 

The simulator supports hardware-software co-design through the ability to produce VCD trace containing signals of custom peripherals and of the ParaNut processor itself.

 

Software debugging is possible using the simulator together with GDB through an OpenOCD-compatible interface.

 

 

You can get ParaNut IP core for free here