This post contains the RiscyOO processor written in Bluespec System Verilog (BSV). RiscyOO implements the RISC-V 64-bit instruction set with the IMAFD extensions, i.e., RV64G. It is a out-of-order superscalar cache-coherent multiprocessor which can boot multicore Linux and AWS F1 FPGA.

 

This processor can be built with a variety of backends for use in different simulation frameworks or FPGA. Currently the supported backends are Connectal and Verilator. Connectal is a generic framework that supports a variety of FPGAs and simulation targets.

 

You can download the Riscy core here