The momentum behind RISC V is growing thanks to the support of technology giants However, it’s also a an obstacle: getting CPU designers to remain on the same page and to avoid the kind of fragmentation that occurred with MIPS as well as Android.

In this regard RISC-V International, the organization that oversees development of the instruction set architecture (ISA) has reached out to the community for advice and guidance on the priorities it should set over the coming years.

The organization published a questionnaire in its list of mailing addresses to gather feedback to “help to identify ISA gaps, develop strategies for the future extension and ensure compatibility between RISC-V applications.”

The goal of this survey is to get an understanding of the projects the group is working on and whether there’s a desire to standardize certain extensions that are being developed in private, RISC-V International chief technology officer Mark Himelstein told The Register.

The RISC-V architecture is often referred to by its name as being”the Linux of chips. It has an array of engineers working together to create the architecture, establish it, and then improve the architecture.

RISC-V is essentially a set of specifications that define how, from a software point of view, compatible CPU cores should operate, such as what types of instructions are available as well as how they’re stored in memory, and other functions central to the system.

These specifications are then royalty-free to use in processors as well as system-on-chips. It’s the responsibility of semiconductor engineers to determine how to organize the plumbing and logic of their chips to run the software developed for RISC V machines.

The RISC-V ISA has a modular design where the ISA comes with a base set of functions, and an array of extensions that can be added, including floating-point math and atomic operations which can be implemented in silicon.

Some extensions are publicly published and then ratified by the community. Engineers are also able to design their own extensions for their specific chips.

Adding functionality, such as instructions for accelerating AI operations, at the CPU core extension level can, depending on the design, avoid the need to develop and hook up separate co-processors and their interfaces.

Chip developers can thus design and implement a variety of proprietary and open extensions for their RISC V CPU cores. That’s why fragmentation can take place.

One company might implementin in its processor family a set of extensions for standard RISC-V and then add a custom, non-standard extension that adds some application specific propriety feature.

Software developed by that company would be unable to run on a different company’s RISC V chips that don’t have that propriety extension since it’s not yet ratified or implemented due to some reason.

The RISC-V International group is determined to stop an uncontrolled growth of ISA by encouraging the groups involved to standardize their extension in an open and co-operative manner, when it’s appropriate to do so.

“A reason for this survey is to determine what else is available. If something is reasonable and is logical, then we can connect people again and reduce the number of non-conforming extensions and not-standard ones,” Himelstein said.

Standardization will allow developers to use RISC V features comfortably since they’ll know their programs will run flawlessly across a wide range available chips. Some companies may still prefer to create their own extensions that are proprietary due to commercial reasons or simply because they’ve come up with something very unique and innovative. This is acceptable by Himelstein as these chips would not run outside software anyways.

“It’s an open culture. If enough people are willing to work together to define an extension’s standard Then it will happen. If not, it won’t happen and people could decide to pursue their own agendas and that’s fine for us.” Himelstein said.

For instance, if the survey is able to demonstrate enough enthusiasm for the support of floating point 8 bits, or FP8 that Nvidia announced last week as a feature for Hopper, its Hopper GPU, RISC-V International will initiate a discussion on the need to standardize this extension. If not, users are free to create their own extensions to it.

“There are other floating point formats available. In the past, we introduced … half-width IEEE floating point. Another one that’s popular , particularly in embedded, is bfloat16 to aid in machine learning. We didn’t manage to get it this year. We’re working to make next year’s deadline,” Himelstein said.

Imagination The company, which licences GPU blueprints to makers of system-on-chips and owns RISC-V compatible CPU designs, said that components which are sold with ratified extensions are crucial to establish a solid RISC V ecosystem.

“Having several custom-made extensions that have not been ratified will hamper the widespread use of RISC-V,” Shreyas Derashri director of Imagination’s department of computing and computing, told The Register. “Imagination is primarily looking to improve the RISC V ecosystem.”

If Imagination develops customized extensions for its customers, the business will collaborate with RISC-V International to have them accepted and ratified. “This includes the work around graphics extensions on RISC-V as well,” Derashri said.

The RISC-V group released 16 specifications last year and there will be more this year, What was proprietary and closed yesterday might be made open for standardization by the community in the coming days. “Just as in Linux the technology that is proprietary today could be a sedimented technology in five , three or two years time,” Himelstein said. “Everybody knows about this game since we’ve lived with this in the computer world for quite a while.”

The RISC-V website also has clear nomenclature on the status of specs under development: whether it’s under discussion, development, public review, frozen, and whether it’s been ratified.

“We’re never going into doing something only to use up the opcode space only to redot again. We could create a fresh extension but like to make sure we do it the right way,” Himelstein said.

Six years were needed for RISCV world to standardize vector specifications. Now RISC-V’s leaders are trying to minimize extension overlap on common functionality, such as matrix operations, which are relevant to the ISA’s special interest groups focusing on graphics and machine learning.

“The vector team is creating a special interest group that will merge with these guys, and then decide what this thing looks like because there’s overlap not only there but in some other places in computer science,” Himelstein said.