PicoRV32 is a CPU core that implements the RISC-V RV32IMC Instruction Set. It can be configured as RV32E, RV32I, RV32IC, RV32IM, or RV32IMC core, and optionally contains a built-in interrupt controller.

 

PicoRV32 is free and open hardware licensed under the ISC license (a license that is similar in terms to the MIT license or the 2-clause BSD license).

 

Features

  • Small (750-2000 LUTs in 7-Series Xilinx Architecture)
  • High fmax (250-450 MHz on 7-Series Xilinx FPGAs)
  • Selectable native memory interface or AXI4-Lite master
  • Optional IRQ support (using a simple custom ISA)
  • Optional Co-Processor Interface

 

This CPU is meant to be used as auxiliary processor in FPGA designs and ASICs. Due to its high fmax it can be integrated in most existing designs without crossing clock domains. When operated on a lower frequency, it will have a lot of timing slack and thus can be added to a design without compromising timing closure.

You can download Picorv32 here