The main motivation for the DarkRISCV was create a migration path for some projects around the 680×0/Coldfire family. Although the code is small and crude when compared with other RISC-V implementations, the DarkRISCV has lots of impressive features:

 

Features

  • implements most of the RISC-V RV32E instruction set
  • implements most of the RISC-V RV32I instruction set (missing csr*, e* and fence*)
  • works up to 250MHz in a ultrascale ku040 (400MHz w/ overclock!)
  • up to 100MHz in a cheap spartan-6, fits in small spartan-3E such as XC3S100E!
  • can sustain 1 clock per instruction most of time (typically 71% of time)
  • flexible harvard architecture (easy to integrate a cache controller, bus bridges, etc)
  • works fine in a real xilinx (spartan-3, spartan-6, spartan-7, artix-7, kintex-7 and kintex ultrascale)
  • works fine with some real altera and lattice FPGAs
  • works fine with gcc 9.0.0 for RISC-V (no patches required!)
  • uses between 850-1500LUTs (core only with LUT6 technology, depending of enabled features and optimizations)
  • optional RV32E support (works better with LUT4 FPGAs)
  • optional 16×16-bit MAC instruction (for digital signal processing)
  • optional coarse-grained multi-threading (MT)
  • no interlock between pipeline stages!
  • BSD license: can be used anywhere with no restrictions.

 

You can download the darkriscv core here