Introduction of the GAP8 IoT application processor

GAP8 is a RISC-V and PULP (Parallel Ultra-Low-Power Processing Platform) open-source platform based IoT application processor. It enables cost-effective development, deployment and autonomous operation of intelligent devices that capture, analyze, classify and act on the fusion of rich data sources such as images, sounds or vibrations. In particular, GAP8 is uniquely optimized to execute a large spectrum of image and audio algorithms including convolutional neural network inference with extreme energy efficiency. This allows industrial and consumer product manufacturers to integrate artificial intelligence and advanced classification into new classes of wireless edge devices for IoT applications including image recognition, counting people and objects, machine health monitoring, home security, speech recognition, consumer robotics and smart toys.

 

GAP8 Micro-architecture

GAP8’s hierarchical, demand-driven architecture enables ultra-low-power operation by combining:

 

  • A series of highly autonomous smart I/O peripherals for connection to cameras, microphones and other capture and control devices.
  • A fabric controller core for control, communications and security functions.
  • A cluster of 8 cores with an architecture optimized for the execution of vectorized and parallelized algorithms combined with a specialized Convolutional Neutral Network accelerator (HWCE).

 

All cores and peripherals are power switchable and voltage and frequency adjustable on demand. DC/DC regulators and clock generators with ultra fast reconfiguration times are integrated. This allows GAP8 to adapt extremely quickly to the processing/energy requirements of a running application. All elements share access to a L2 memory area. The cluster cores and HWCE share access to a L1 memory area and instruction cache. Multiple DMA units allow autonomous, fast, low power transfers between memory areas. A memory protection unit is included to allow secured execution of applications on GAP8.

 

All 9 cores share the same extended RISC-V instruction set architecture. The I (integer), C (compressed instruction), M (Multiplication and division) extensions and a portion of the supervisor ISA subsets are supported. These are extended with specific instructions to optimize the algorithms that GAP8 is targeted at. These extensions include zero overhead hardware loops, pointer post/pre modified memory accesses, instructions mixing control flow with computation (min, max, etc), multiply/subtract and accumulate, vector operations, fixed point operations, bit manipulation and dot product. All of these instruction extensions are optimized by the compiler or can be used ‘by hand’.

 

GAP8 Features
  • 1+8 high performance extended RISC-V ISA based cores.
    • 1 – A high performance micro-controller
    • 8 – 8 cores that execute in parallel for compute intensive tasks
  • A hardware Convolution Engine (HWCE) for Convolutional Neural Networks based applications.
  • A level 2 Memory (512KB) for all the cores
  • A level 1 Memory (64 KB) shared by all the cores in Cluster
  • A level 1 memory (8 KB) owned by FC
  • A smart, lightweight and completely autonomous DMA (micro-DMA) capable of handling complex I/O schemes.
  • A multi-channel 1D/2D cluster-DMA controls the transactions between the L2 Memory and L1 Memory.
  • A rich set of peripheral interface
  • 2 programmable clocks
  • Memory Protection Unit

 

You can check out the GAP8 Core here